CH340 Selector – CH340G vs C vs E vs B, Pinout & 3.3 V Use

Answer

CH340G needs a 12 MHz crystal (33 pF load caps) and is rated −40 to 85 °C with TX baud error under 0.3%. CH340C uses the same SOP-16 footprint with a built-in clock, but it is rated −20 to 70 °C with TX error under 1.8%, and its pin 8 is OUT#, not a crystal pin. CH340E is a 10-pin MSOP with no DTR#. CH340B adds an EEPROM for custom strings and IDs. Source: WCH CH340DS1, Version 3D, §3–§7.

Calculator

Temperature min (°C) Temperature max (°C) Supply MCU baud error (%) Baud rate (bps) Duplex, if baud is set

Recommended: CH340C
Pins versus CH340G: Same SOP-16 pins 1–6 and 9–16. Pin 7 is NC (leave open). Pin 8 is OUT#, not XO — remove the crystal and both capacitors.

fail CH340G: Needs a 12 MHz crystal and two 33 pF capacitors. Reference SOP-16. Crystal on pin 7 (XI) and pin 8 (XO), with two 33 pF load capacitors.
fail CH340T: Needs a 12 MHz crystal and two 33 pF capacitors. SSOP-20, not the CH340G SOP-16 footprint. Still needs a 12 MHz crystal and two 33 pF capacitors.
pass CH340C: SOP-16 with a built-in clock and DTR#. Rated −20 to 70 °C, TX error under 1.8 %. 5 V mode is 4.0–5.3 V, with V3 decoupled by 0.1 µF. Same SOP-16 pins 1–6 and 9–16. Pin 7 is NC (leave open). Pin 8 is OUT#, not XO — remove the crystal and both capacitors.
pass CH340B: SOP-16 with an internal EEPROM for a custom serial or product string. 5 V mode is 4.0–5.3 V, with V3 decoupled by 0.1 µF. SOP-16, but pin 7 is RST#, pin 8 is NC, and pin 15 is TNOW rather than R232.
fail CH340E: No DTR#. New MSOP-10 layout. No DTR#, DSR#, RI# or DCD#. V3 is pin 10. Auto-reset has to use RTS#.
fail CH340X: No DTR#. MSOP-10, same missing modem lines as CH340E. Adds 5 V-tolerant I/O when the supply is 3.3 V.
fail CH340N: No DTR#. RTS#/CTS# are not confirmed for this package. SOP-8 is a new layout. This page does not treat it as having modem or RTS#/CTS# pins.
fail CH340K: No DTR#. RTS#/CTS# are not confirmed for this package. ESSOP-10 is a new layout. This page does not treat it as having modem or RTS#/CTS# pins.

How it works

Below −20 °C or above 70 °C, only CH340G and CH340T stay inside the datasheet ambient range. CH340R is in that wide-temperature group and is discontinued, so the selector does not offer it. Crystal-free parts are C, N, K, E, X and B. CH340E (and CH340X, which WCH describes as a CH340E with 5 V-tolerant I/O at 3.3 V) omit DTR#, DSR#, RI# and DCD#. A custom serial or product string needs the CH340B EEPROM.

At 3.3 V, tie V3 to VCC. G/T/R allow 2.9–3.6 V. The crystal-free parts allow 3.1–3.6 V. Budget the 3.3 V maximum current from §6.3 (12 mA, or 9 mA on CH340B), not a scaled 5 V figure.

The baud screen adds the MCU’s transmit error to the CH340 TX error and compares the sum with the about 2% receive tolerance in §5.4. It is a screening estimate. Check the MCU’s own receive tolerance. From −25 to 75 °C the internal clock may be off by up to ±1.8%, which already uses most of that 2% window.

Pins that differ from a CH340G layout (SOP-16)

Pin	CH340G	CH340C	CH340B
7	XI (crystal)	NC, leave open	RST#
8	XO (crystal)	OUT# (active low)	NC
15	R232	R232	TNOW

All other SOP-16 pins match across the three: 1 GND, 2 TXD, 3 RXD, 4 V3, 5 UD+, 6 UD−, 9 CTS#, 10 DSR#, 11 RI#, 12 DCD#, 13 DTR#, 14 RTS#, 16 VCC. CH340E (MSOP-10) is 1 UD+, 2 UD−, 3 GND, 4 RTS#, 5 CTS#, 6 TNOW, 7 VCC, 8 TXD, 9 RXD, 10 V3.

Part numbers

CH340G, CH340C and CH340B (SOP-16). CH340N (SOP-8). CH340K (ESSOP-10). CH340E and CH340X (MSOP-10). CH340T (SSOP-20). Information only.

Disclaimer

Data comes from the WCH CH340DS1 datasheet (Version 3D) as read on 26 Oct 2026. Older copies (for example v2C) list different capacitor, supply and baud-error values. Use the current WCH file. Lot-dependent features are not guaranteed. Validate on your own hardware.

Updated: 2026-10-26 · Jasper

Parameters used on this page

Parameter	Value	Source
Packages	G/C/B SOP-16; N SOP-8; K ESSOP-10; E/X MSOP-10; T/R SSOP-20	CH340DS1 V3D §3 p.2
Ambient temperature	G/T/R −40 to 85 °C; C/N/K/E/X/B −20 to 70 °C	§6.1 p.8
VCC, 5 V mode	4.0–5.3 V; ICC 7 typ / 20 mA max (CH340B 6 / 15 mA)	§6.2 p.8
VCC, 3.3 V mode (V3 = VCC)	G/T/R 2.9–3.6 V; C/N/K/E/X/B 3.1–3.6 V; ICC 4 typ / 12 mA max (CH340B 3 / 9 mA)	§6.3 pp.8–9
TX baud error	G/T/R under 0.3%; C/N/K/E/X/B under 1.8%	§5.4 p.7
RX tolerance	about 2%	§5.4 p.7
Internal clock error	±1.2% from −5 to 55 °C; ±1.8% from −25 to 75 °C	§6.4 p.9
External clock (G/T/R)	11.98–12.02 MHz; crystal load caps 33 pF (a ceramic resonator usually 47 pF)	§6.4 p.9; §7.1 p.10
Baud range	50 bps–2 Mbps. Above 1 Mbps one-way or 500 kbps two-way, WCH recommends CH343.	p.1; §5.4 p.7
CH340B default IDs	VID 1A86h / PID 7523h (EEPROM default)	§5.2 p.6
V3 pin	5 V: 0.1 µF to GND. 3.3 V: tie V3 to VCC.	p.3 pin table

Worked examples

If the far-end MCU already has 1.5% baud error, the worst-case mismatch is 3.3% with CH340C and 1.8% with CH340G. Against a receive tolerance of about 2%, CH340C fails that screen and CH340G passes. An indoor Arduino-style board that needs auto-reset points to CH340C. An outdoor device at −30 °C points to CH340G plus a 12 MHz crystal and two 33 pF capacitors. TXD/RXD/RTS#/CTS# in the smallest package points to CH340E. Boards that must show distinct serial strings point to CH340B.

Pitfalls

Leaving pin 8 tied to crystal parts when moving from G to C. On CH340C, pin 8 is OUT#, so remove the crystal and both caps. WCH says a 4.7 kΩ pull-down makes pin 8 a second open-drain DTR# only on CH340C lots whose number starts with 4 and ends above B40 (§5.3 p.7). Check the lot code. This page has not tested that on hardware.
Using C, N, K, E, X or B outdoors. They are rated only −20 to 70 °C.
Expecting DTR# on CH340E. It has none, so auto-reset must use RTS#.
Forgetting V3. At 3.3 V tie V3 to VCC. At 5 V, decouple V3 with 0.1 µF. CH340E has V3 on pin 10.
Swapping CH340B for G pin-for-pin. Pin 7 is RST# and pin 15 is TNOW.
Driving DTR# hard at power-up. Before USB enumeration, DTR# is read as a configuration input (§5.1 p.5).
Copying 22 pF from old notes. The current datasheet specifies 33 pF for a crystal.

FAQ

What is the difference between CH340G and CH340C?

Same SOP-16 footprint. C has a built-in clock (no crystal), a −20 to 70 °C rating and TX error under 1.8%, and its pin 8 is OUT#.

Does CH340C need a crystal?

No. Pin 7 is NC. Pin 8 is OUT#.

Does CH340E have DTR?

No. It has RTS# and CTS#. Use RTS# for auto-reset.

Can CH340 run at 3.3 V?

Yes, with V3 tied to VCC: 2.9–3.6 V for G/T/R and 3.1–3.6 V for C/N/K/E/X/B.

What crystal does CH340G use?

12 MHz with two 33 pF capacitors (WCH §7.1).

Which CH340 works at −40 °C?

CH340G and CH340T. CH340R is discontinued.

Sources

WCH CH340DS1, Version 3D. Download page https://www.wch-ic.com/downloads/CH340DS1_PDF.html (lists file version 3.4, 2025-03-12). PDF https://www.wch-ic.com/download/file?id=79 (retrieved 2026-10-26).
Updated: 2026-10-26. Jasper.