A tactile switch does not close once. Contacts chatter for a millisecond or more. Firmware that looks at a raw GPIO on every bounce sees extra edges. Hardware RC plus a Schmitt-trigger input is one way to swallow that chatter; polling the resulting bit is another. They are not the same delay.
Charge is not 1τ
For a pull-up R and capacitor C, voltage toward VCC is the UM10204 §7.1 exponential V(t) = VCC (1 − e^{−t/RC}). Time from 0 V to a rising threshold VT+ is
t = −R C ln(1 − VT+/VCC)
At VT+ = 0.7 VCC this is −ln(0.3) τ ≈ 1.204 τ, not 1τ. 10 kΩ × 100 nF is 1.204 ms; 39 kΩ is 4.695 ms. The switch debounce calculator prints that crossing, not a 1τ heuristic.
Press and release are different paths
Release (switch open) charges through the pull-up. Press (active-low closed) discharges through whatever is between the node and ground. If that series resistance Rd is zero, the model is an ideal short: voltage drops immediately. Using the same R for both directions is a fake symmetric RC. MCU internal pull-ups in the 20–50 kΩ band are a user scenario you type, not a clamp the calculator applies for you.
Hysteresis memory
A Schmitt input, as in TI SCEA046B, switches high when the analog rise crosses VT+ and low when the fall crosses VT−, and holds in between. A raw comparator at the midpoint has no memory, so a slow charge or a bounce through the band chatters. SLLA364A is the reminder that a slow RC edge is not certified safe on a GPIO that is not actually a Schmitt input. CD74HC14 Rev. G VT+/VT− numbers are a labelled datasheet example, not automatic limits.
Firmware still has a sample clock
Polling the Schmitt bit at period Ts, phase φ, and accepting after N consecutive equal samples adds latency that depends on phase. Miss the first stable window and you wait another period. Interrupts, NRST, encoders, and double-click are out of scope here.
Use the calculator to put analog, Schmitt, raw, and firmware on the same synthetic bounce. It is a model, not a lab capture.