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Switch Debounce Calculator

t = -RC ln(1 - VT+/VCC). 10 kΩ × 100 nF to 0.7 VCC is 1.204 ms.

By Jasper · Updated

Calculator

PASScharge to VT+ 1.204 msτcharge 1 ms · Rd ideal short

Active-low SPST only. Same synthetic bounce on analog RC, Schmitt, raw midpoint, and firmware poll. Not a lab capture. Rd = 0 is an ideal short.

MCU internal pull-up scenario (still editable):

Synthetic bounce (t in ms, closed = pressed)
t (ms)Closed

Press discharges through an ideal short (Rd = 0). Release charges through R. Paths are not symmetric.

τ charge
1 ms
τ discharge
ideal short
t to VT+
1.204 ms
t to VT−
instant
Schmitt press
0 ns
Schmitt release
—
Firmware press
1 ms
Firmware release
—
Firmware stable
yes
R
10 kΩ
C
100 nF
VT+
2.31 V
VT−
0.99 V
  • Warn Synthetic bounce: Timeline is an editable synthetic bounce, not a lab capture.
  • Warn Slow-edge CMOS: SLLA364A / SCEA046B: a slow RC edge is not certified safe on a non-Schmitt GPIO. Thresholds are the numbers you typed, not a CD74HC14 min/max.
  • Pass Charge vs discharge: Press discharges through an ideal short (Rd = 0). Release charges through Rpullup. Paths are not symmetric.
  • Pass Firmware poll stability: Accepted after 2 consecutive sample(s) at period 0.001 s, phase 0 s.
  • Pass Internal pull-up scenario: Rpullup is whatever you typed; 20–50 kΩ is only a common MCU internal-pull-up scenario.
Breadboard active-low SPST debounce: R 10 kΩ, C 100 nF, Rd ideal short, switch released (open) on 3.3 V Active-low SPST to GND, RC node into a Schmitt GPIO. Charge through R, discharge through ideal short. Synthetic breadboard, not a lab capture. R 10 kΩ brown, black, orange, gold SW open Schmitt VT+ 2.31 V VT− 0.99 V R 10 kΩ C 100 nF ideal short VCC 3.3 V GND GPIO
SPST bounce: analog, Schmitt, raw, firmware Synthetic active-low bounce on analog RC, Schmitt, raw midpoint, and firmware poll. Horizontal axis is t (ms); analog vertical axis is V (V); logic lanes are 0/1. VT+ 2.31 V, VT− 0.99 V. Left and Right arrows move the cursor along the x-axis; Home and End jump to the ends. Hold Shift for a finer step. 0123V (V)LHSchmittLHRawLHFirmware0510t (ms) VT+VT−t=0t=0t=0t=0
Same synthetic bounce on analog RC, Schmitt hysteresis, raw midpoint, and firmware poll. Not a lab capture. VT+/VT− marks are the numbers you typed.

Formula

Charge to VT+

t=-RCln(1-VT+/VCC) t = -R C ln(1 - VT+/VCC)

Discharge to VT−

td=-RdCln(VT-/VCC) td = -Rd C ln(VT-/VCC) (Rd = 0 → instant)

Schmitt hysteresis

ΔVT=VT+-VT- ΔVT = VT+ - VT-

Variables

Symbol Meaning Unit Typical range Precision Default
VCC Supply V ≥ 0 V 4 sig 3.3 V
R Pull-up Ω ≥ 0 mΩ 4 sig 10 kΩ
C Capacitor F ≥ 0 pF 4 sig 100 nF
Rd Discharge resistance (0 = ideal short) Ω ≥ 0 mΩ 4 sig 0 mΩ
VT+ Rising threshold V ≥ 0 V 4 sig 2.31 V
VT- Falling threshold V ≥ 0 V 4 sig 0.99 V
SW0 Initial switch closed — — 1 sig 0
Ts Firmware sample period s ≥ 0 ns 4 sig 1 ms
φ Firmware sample phase s ≥ 0 ns 4 sig 0 ns
N Consecutive samples to accept — ≥ 1 1 sig 2
t Charge time 0 → VT+ s — 4 sig —
td Discharge time VCC → VT− s — 4 sig —
ΔVT Hysteresis VT+ − VT− V — 4 sig —
τc Charge time constant s — 4 sig —

Worked example

10 kΩ × 100 nF to 0.7 VCC

Input Value
VCC · Supply 3.3 V
R · Pull-up 10 kΩ
C · Capacitor 100 nF
Rd · Discharge resistance (0 = ideal short) 0 mΩ
VT+ · Rising threshold 2.31 V
VT- · Falling threshold 0.99 V
SW0 · Initial switch closed no
Ts · Firmware sample period 1 ms
φ · Firmware sample phase 0 ns
N · Consecutive samples to accept 2
Output Value
t · Charge time 0 → VT+ 1.204 ms
τc · Charge time constant 1 ms
ΔVT · Hysteresis VT+ − VT− 1.32 V

39 kΩ × 100 nF to 0.7 VCC

Input Value
VCC · Supply 3.3 V
R · Pull-up 39 kΩ
C · Capacitor 100 nF
Rd · Discharge resistance (0 = ideal short) 0 mΩ
VT+ · Rising threshold 2.31 V
VT- · Falling threshold 0.99 V
SW0 · Initial switch closed no
Ts · Firmware sample period 1 ms
φ · Firmware sample phase 0 ns
N · Consecutive samples to accept 2
Output Value
t · Charge time 0 → VT+ 4.695 ms
τc · Charge time constant 3.9 ms

How it works

Mechanical switches bounce. An active-low SPST to ground with a pull-up and a capacitor is a first-order RC: release charges through R toward VCC, press discharges through Rd (or an ideal short). A Schmitt input remembers the last state between VT− and VT+; a raw midpoint comparator does not. Firmware that polls that Schmitt bit still needs N consecutive samples.

This page runs all four methods on one synthetic bounce timeline you can edit. Thresholds are yours. They are not a CD74HC14 test limit and not a scope capture.

Pitfalls

  • A 1τ heuristic is not the VT+ crossing. t = −RC ln(1 − VT+/VCC).
  • Charge (release through R) and discharge (press through Rd) are not symmetric. Rd = 0 is an ideal short, not a fake matching RC.
  • VT+/VT− are the numbers you typed. They are not CD74HC14 min/max and do not certify a slow edge on a non-Schmitt GPIO (SLLA364A / SCEA046B).
  • The bounce table is synthetic and editable. It is not a captured waveform, and this page does not cover encoders or double-click.

FAQ

Why not wait one time constant?

1τ is ~63 % of VCC. VT+ = 0.7 VCC is −ln(0.3) τ ≈ 1.204 τ. The calculator prints that exponential, not a 1τ rule of thumb.

What does Rd = 0 mean?

An ideal switch short to ground. Press voltage drops immediately. Real switches have milliohms plus inductance; type a series Rd if you want a finite discharge.

Is a slow RC edge safe on any GPIO?

No. SLLA364A and SCEA046B discuss slow edges and Schmitt inputs. This page does not certify a non-Schmitt pin.

Does firmware sample the analog voltage?

No. It samples the Schmitt lane at phase + k × period and accepts after N consecutive equal samples.

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